CAT1021: CPU Supervisor with 2 k EEPROM Memory
Description: The CAT1021 is a complete memory and supervisory s...
The CAT1021 is a complete memory and supervisory solution for microcontroller based systems. A 2 k-bit serial EEPROM memory and a system power supervisor with brown-out protection are integrated together in low power CMOS technology. Memory interface is via a 400 kHz I²C bus.
The CAT1021 provides a precision VCC sense circuit and two open drain outputs: one (RESET) drives high and the other (RESET) drives low whenever VCC falls below the reset threshold voltage. The CAT1021 also has a Write Protect input (WP). Write operations are disabled if WP is connected to a logic high.
The supervisor has a 1.6 second watchdog timer circuit that resets a system to a known state if software or a hardware glitch halts or 'hangs' the system. The watchdog timer monitors the SDA signal.
The power supply monitor and reset circuit protect memory and system controllers during power up/down and against brownout conditions. Five reset threshold voltages support 5.0 V, 3.3 V and 3.0 V systems. If power supply voltages are out of tolerance reset signals become active, preventing the system microcontroller, ASIC or peripherals from operating. Reset signals become inactive typically 200 ms after the supply voltage exceeds the reset threshold level. With both active high and low reset signals, interface to microcontrollers and other ICs is simple. In addition, the RESET pin or a separate input, MR, can be used as an input for push-button manual reset capability.
The on-chip, 2 k-bit EEPROM memory features a 16-byte page. In addition, hardware data protection is provided by a VCC sense circuit that prevents writes to memory whenever VCC falls below the reset threshold or until VCC reaches the reset threshold during power up.
Available packages include an 8-pin DIP, 8-pin SOIC, 8-pin TSSOP, 8-pin TDFN and 8-pin MSOP. The TDFN packa
Precision power supply voltage monitor
- 5.0 V, 3.3 V and 3.0 V systems
- Five threshold voltage options
Active high or low reset
- Valid reset guaranteed at VCC = 1 V
400 kHz I²C bus
3.0 V to 5.5 V operation
Low power CMOS technology
16-Byte page write buffer
Built-in inadvertent write protection
— WP pin
1,000,000 Program/Erase cycles
Manual reset input
100 year data retention
8-pin DIP, SOIC, TSSOP, MSOP or TDFN
(3 x 3 mm foot-print) packages
— TDFN max height is 0.8mm
Industrial and extended temperature ranges
Technical Documentation & Design Resources
Product Change Notification
256 x 8
Data Transmission Standard:
fcycle Max (kHz):
tACC Max ns:
VCC Min (V):
VCC Max (V):
Istandby Max (µA):
Iact Max (mA):
T Min (°C):
T Max (°C):