MC100E431: ECL 3-Bit Differential D Flip-Flop

Description: The MC10E/100E431 is a 3-bit flip-flop with differ...
  • The MC10E/100E431 is a 3-bit flip-flop with differential clock, data input and data output.

    The asynchronous Set and Reset controls are edge-triggered rather than level controlled. This allows the user to rapidly set or reset the flip-flop and then continue clocking at the next clock edge, without the necessity of de-asserting the set/reset signal (as would be the case with a level controlled set/reset).

    The E431 is also designed with larger internal swings, an approach intended to minimize the time spent crossing the threshold region and thus reduce the metastability susceptibility window.

    The differential input structures are clamped so that the inputs of unused registers can be left open without upsetting the bias network of the device. The clamping action will assert the Dbar and the CLKbar sides of the inputs. Because of the edge triggered flip-flop nature of the device simultaneously opening both the clock and data inputs will result in an output which reaches an unidentified but valid state. Note that the input clamps only operate when both inputs fall to 2.5 V below VCC.

    The 100 Series contains temperature compensation.

    The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 µF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.
  • Features
  • Edge-Triggered Asynchronous Set and Reset
  • Differential D, CLK and Q; VBB Reference Available
  • 1100MHz Min. Toggle Frequency
  • PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V
  • Internal Input Pulldown Resistors
  • ESD Protection: > 1 kV HBM, > 75 V MM
  • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
  • Moisture Sensitivity Level 1
    For Additional Information, see Application Note AND8003/D
  • Flammability Rating: UL-94 code V-0 @ 1/8",Oxygen Index 28 to 34
  • Transistor Count = 348 devices
  • Pb-Free Packages are Available
  • Technical Documentation & Design Resources
    Product Change Notification
    Availability and Samples
    MC100E431FNR2G
  • Status: Active
  • Compliance: Pb-free Halide free 
  • Description: ECL 3-Bit Differential D Flip-Flop
  • Package Type: PLCC-28
  • Package Case Outline: 776-02
  • MSL: 3
  • Container Type: REEL
  • Container Qty: 500
  • Packages
    Specifications
  • Type: D-Type 
  • Bits:
  • Input Level: ECL 
  • Output Level: ECL 
  • VCC Typ (V):
  • tJitter Typ (ps):
  • tpd Typ (ns): 0.7 
  • tsu Min (ns): 0.2 
  • th Min (ns): 0.2 
  • trec Typ (ns): 0.4 
  • tR & tF Max (ps): 700 
  • fToggle Typ (MHz): 1100 
  • Package Type: PLCC-28 
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