MC100EP196: 3.3 V ECL Programmable Delay Chip

Description: The MC100EP196 is a programmable delay chip (PDC) ...
  • The MC100EP196 is a programmable delay chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides programmably variable delay of a differential ECL input signal. It has similar architecture to the EP195 with the added feature of further tuneability in delay using the FTUNE pin. The FTUNE input takes an analog voltage from VCC to VEE to fine tune the output delay from 0 to 60 ps.
  • Features
  • Maximum Frequency > 1.2 GHz Typical
  • PECL Mode Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.6 V
  • Open Input Default State
  • Safety Clamp on Inputs
  • A Logic High on the ENbar Pin Will Force Q to Logic Low
  • D[0:10] Can Accept Either ECL, LVCMOS, or LVTTL Inputs
  • VBB Output Reference Voltage
  • Pb-Free Packages are Available
  • Technical Documentation & Design Resources
    Product Change Notification
    Availability and Samples
    MC100EP196FAG
  • Status: Active
  • Compliance: Pb-free Halide free 
  • Description: 3.3 V ECL Programmable Delay Chip
  • Package Type: LQFP-32
  • Package Case Outline: 
  • MSL: 2
  • Container Type: JTRAY
  • Container Qty: 250
  • Inventory

  • Market Leadtime (weeks):2 to 4
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  • MC100EP196FAR2G
  • Status: Active
  • Compliance: Pb-free Halide free 
  • Description: 3.3 V ECL Programmable Delay Chip
  • Package Type: LQFP-32
  • Package Case Outline: 
  • MSL: 2
  • Container Type: REEL
  • Container Qty: 2000
  • Packages
    Specifications
  • Input Level: CML  ECL 
  • Output Level: ECL 
  • VCC Typ (V): 3.3 
  • fMax Typ (MHz): 1200 
  • td(prog) Min (ns): 8.6 
  • td(prog) Max (ns): 12 
  • td(step) Typ (ps): 11 
  • tJitter Typ (ps):
  • tR & tF Max (ps): 200 
  • Package Type: LQFP-32 
  • ON Semiconductor Full Web Site