MC100LVELT20: LVTTL/LVCMOS to Differential LVPECL Translator

Description: The MC100LVELT20 is a 3.3 V TTL/CMOS to differenti...
  • The MC100LVELT20 is a 3.3 V TTL/CMOS to differential PECL translator. Because PECL (Positive ECL) levels are used, only +3.3 V and ground are required. The small outline SOIC−8 package and the single gate of the MC100LVELT20 makes it ideal for those applications where space, performance, and low power are at a
    premium.
    The 100 Series contains temperature compensation.
  • Features
  • 390 ps Typical Propagation Delay
  • Maximum Input Clock Frequency > 0.8 GHz Typical
  • Operating Range VCC = 3.0 V to 3.6 Vwith GND = 0 V
  • PNP TTL Input for Minimal Loading
  • Pb-Free Packages are Available
  • Applications
  • Single ended to differential level translation.
  • Technical Documentation & Design Resources
    Product Change Notification
    Availability and Samples
    MC100LVELT20DG
  • Status: Active
  • Compliance: Pb-free Halide free 
  • Description: LVTTL/LVCMOS to Differential LVPECL Translator
  • Package Type: SOIC-8
  • Package Case Outline: 751-07
  • MSL: 1
  • Container Type: TUBE
  • Container Qty: 98
  • Inventory

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  • MC100LVELT20DR2G
  • Status: Active
  • Compliance: Pb-free Halide free 
  • Description: LVTTL/LVCMOS to Differential LVPECL Translator
  • Package Type: SOIC-8
  • Package Case Outline: 751-07
  • MSL: 1
  • Container Type: REEL
  • Container Qty: 2500
  • Inventory

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  • Packages
    Specifications
  • Channels:
  • Input Level: CMOS  TTL 
  • Output Level: ECL 
  • VCC Typ (V): 3.3 
  • fMax Typ (MHz): 1000 
  • tpd Typ (ns): 0.37 
  • tR & tF Max (ps): 225 
  • Package Type: SOIC-8 
  • ON Semiconductor Full Web Site