MC10E143: 5.0 V ECL 9-Bit Hold Register

Description: The MC10E/100E143 is a 9-bit holding register, des...
  • The MC10E/100E143 is a 9-bit holding register, designed with byte-parity applications in mind. The E143 holds current data or loads new data, with the nine inputs D0-D8 accepting parallel input data.

    The SEL (Select) input pin is used to switch between the two modes of operation HOLD and LOAD. Input data is accepted by the registers a set-up time before the positive going edge of CLK1 or CLK2. A HIGH on the Master Reset pin (MR) asynchronously resets all the registers to zero.

    The 100 Series contains temperature compensation.
  • Features
  • 700MHz Min. Operating Frequency
  • 9-Bit for Byte-Parity Applications
  • Asynchronous Master Reset
  • Dual Clocks
  • PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V
  • 75kW Input Pulldown Resistors
  • NECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V
  • Internal Input Pulldown Resistors
  • ESD Protection: > 2 KV HBM, > 200 V MM
  • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
  • Moisture Sensitivity Level 1
    For Additional Information, see Application Note AND8003/D
  • Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
  • Transistor Count = 484 devices
  • Pb-Free Packages are Available
  • Technical Documentation & Design Resources
    Product Change Notification
    Availability and Samples
    MC10E143FNR2G
  • Status: Active
  • Compliance: Pb-free Halide free 
  • Description: 5.0 V ECL 9-Bit Hold Register
  • Package Type: PLCC-28
  • Package Case Outline: 776-02
  • MSL: 3
  • Container Type: REEL
  • Container Qty: 500
  • Packages
    Specifications
  • Type: Register 
  • Bits:
  • Input Level: ECL 
  • Output Level: ECL 
  • VCC Typ (V):
  • tJitter Typ (ps):
  • tpd Typ (ns): 0.8 
  • tsu Min (ns): 0.05 
  • th Min (ns): 0.3 
  • trec Typ (ns): 0.7 
  • tR & tF Max (ps): 800 
  • fToggle Typ (MHz): 900 
  • Package Type: PLCC-28 
  • ON Semiconductor Full Web Site