MC10E451: 5.0 V ECL 6-Bit D Register Differential Data and Clock
Description: The MC10E/100E451 contains six D-type flip-flops w...
The MC10E/100E451 contains six D-type flip-flops with single-ended outputs and differential data inputs. The common clock input is also differential. The registers are triggered by a positive transition of the positive clock (CLK) input.
A HIGH on the Master Reset (MR) input resets all Q outputs to LOW.
The differential input structures are clamped so that the inputs of unused registers can be left open without upsetting the bias network of the device. The clamping action will assert the Dbar and the CLKbar sides of the inputs. Because of the edge triggered flip-flop nature of the device simultaneously opening both the clock and data inputs will result in an output which reaches an unidentified but valid state. Note that the input clamps only operate when both inputs fall to 2.5 V below VCC.
The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.
The 100 Series contains temperature compensation.
Differential Inputs: Data and Clock
1100MHz Min. Toggle Frequency
Asynchronous Master Reset
PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V
Internal Input Pulldown Resistors
ESD Protection: > 2 kV HBM, > 200 V MM
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
Transistor Count = 348 devices
Pb-Free Packages are Available
Technical Documentation & Design Resources
Product Change Notification
Availability and Samples
Compliance: Pb-free Halide free
Description: 5.0 V ECL 6-Bit D Register Differential Data and Clock
Package Type: PLCC-28
Package Case Outline: 776-02
Container Type: REEL
Container Qty: 500
VCC Typ (V):
tJitter Typ (ps):
tpd Typ (ns):
tsu Min (ns):
th Min (ns):
trec Typ (ns):
tR & tF Max (ps):
fToggle Typ (MHz):