MC100EL35: ECL JK Flip-Flop

Description: The MC10EL/100EL35 is a high speed JK flip-flop. T...
  • The MC10EL/100EL35 is a high speed JK flip-flop. The J/K data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The reset pin is asynchronous and is activated with a logic HIGH.

  • Features
  • 525ps Propagation Delay
  • 2.2GHz Toggle Frequency
  • ESD Protection: > 1 kV HBM, > 100 V MM
  • PECL Mode Operating Range: VCC= 4.2 V to 5.7 with VEE= 0 V
  • NECL Mode Operating Range: VCC= 0 V with VEE= -4.2 V to -5.7 V
  • Internal Input Pulldown Resistors on J, K, CLK, and R
  • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
  • Moisture Sensitivity Level 1
    For Additional Information, see Application Note AND8003/D
  • Flammability Rating: UL-94 V-0 @ 0.125 in, Oxygen Index: 28 to 34
  • Transistor Count = 81 devices
  • Pb-Free Packages are Available
  • Applications
  • Timing Circuits
  • Technical Documentation & Design Resources
    Product Change Notification
    Availability and Samples
    MC100EL35DG
  • Status: Lifetime
  • Compliance: Pb-free Halide free 
  • Description: ECL JK Flip-Flop
  • Package Type: SOIC-8
  • Package Case Outline: 751-07
  • MSL: 1
  • Container Type: TUBE
  • Container Qty: 98
  • Inventory

  • Market Leadtime (weeks):Contact Factory
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