MC100EL38: 5.0 V ECL ÷2, ÷4, ÷8 Clock Generation Chip

Description: The MC100EL38 is a low skew divide by 2, divide by...
  • The MC100EL38 is a low skew divide by 2, divide by 4/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal.

    The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.

    The common enable (ENbar) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input.

    The Phase_Out output will go HIGH for one clock cycle whenever the divide by 2 and the divide by 4/6 outputs are both transitioning from a LOW to a HIGH. This output allows for clock synchronization within the system.

    Upon startup, the internal flip-flops will attain a random state; therefore, for systems which utilize multiple EL38s, the master reset (MR) input must be asserted to ensure synchronization. For systems which only use one EL38, the MR pin need not be exercised as the internal divider design ensures synchronization bet
  • Features
  • 50 ps Output-to-Output Skew
  • Synchronous Enable/Disable
  • Master Reset for Synchronization
  • ESD Protection: > 2 KV HBM, > 100 V MM
  • The 100 Series Contains Temperature Compensation
  • PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V
  • Internal Input Pulldown Resistors on CLK, ENbar, MR, and DIVSEL
  • Q Output will Default LOW with Inputs Open or at VEE
  • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
  • Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
  • Transistor Count = 388 devices
  • Pb-Free Packages are Available
  • Technical Documentation & Design Resources
    Product Change Notification
    Availability and Samples
  • Status: Active
  • Compliance: Pb-free Halide free 
  • Description: 5.0 V ECL ÷2, ÷4, ÷8 Clock Generation Chip
  • Package Type: SOIC-20W
  • Package Case Outline: 751D-05
  • MSL: 3
  • Container Type: REEL
  • Container Qty: 1000
  • Packages
  • Type: Divider 
  • Input Level: ECL 
  • Output Level: ECL 
  • VCC Typ (V):
  • fMax Typ (MHz): 1200 
  • tpd Typ (ns): 0.9 
  • tR & tF Max (ps): 550 
  • Package Type: SOIC-20W 
  • ON Semiconductor Full Web Site