NB7L32M: ÷·2 Divider with CML Output
Description: The NB7L32M is an integrated /2 divider with diffe...
The NB7L32M is an integrated /2 divider with differential clock inputs and asynchronous reset.
Differential clock inputs incorporate internal 50 Ω termination resistors and accept LVPECL (Positive ECL), CML, or LVDS. The high frequency reset pin is asserted on the rising edge. Upon power-up, the internal flip-flops will attain a random state; the reset allows for the synchronization of multiple NB7L32M's in a system.
The differential 16 mA CML output provides matching internal 50 Ω termination which guarantees 400 mV output swing when externally receiver terminated 50 Ω to VCC (See Figure 16).
The device is housed in a small 3x3 mm 16 pin QFN package.
Maximum Input Clock Frequency 14 GHz Typical
200 ps Max Propagation Delay
30 ps Typical Rise and Fall Times
< 0.5 ps Maximum (RMS) Random Clock Jitter
Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V
CML Output Level (400 mV Peak-to-Peak Output), Differential Output Only
50 Ω Internal Input and Output Termination Resistors
Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP, EP, and SG Devices
Full RoHS Compliance.
High frequency clock division in Automated Test Equipment.
Ultra precise clock division in networking and telecomm applications.
Technical Documentation & Design Resources
Evaluation/Development Tool Information
Product Change Notification
Availability and Samples
Compliance: Pb-free Halide free
Description: ÷·2 Divider with CML Output
Package Type: QFN-16
Package Case Outline: 485G-01
Container Type: TUBE
Container Qty: 123
Market Leadtime (weeks):2 to 4
VCC Typ (V):
fMax Typ (MHz):
tpd Typ (ns):
tR & tF Max (ps):